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Developer Divyansh Agrawal reports building Qwenputer, an experimental version of Qwen3.5 4B with a compiled 32-bit RISC-V CPU operating inside the model’s forward passes. The design uses Gated DeltaNet state as addressable memory; Agrawal says it passed official RISC-V tests and completed an 18-million-instruction run without error. Those results are the creator’s reported tests, not an independent evaluation.
Developer Divyansh Agrawal says he has built Qwenputer, an experimental version of Qwen3.5 4B that runs a compiled 32-bit RISC-V CPU inside the model’s forward passes. Rather than calling an external processor or software tool, the design uses the model’s Gated DeltaNet state as addressable memory, a demonstration of how neural-network layers can be configured to execute deterministic computing steps.
Agrawal describes Qwenputer as a stock Qwen3.5 4B model with additional CPU weights. The processor is an RV32IM core, with the Zba extension and a small unit for larger-number arithmetic. It occupies 11 layers placed before the model’s original 32 layers. Agrawal says the original model weights remain unchanged, with the computer weights added on top.
The memory mechanism is based on Gated DeltaNet (GDN), a recurrent attention mechanism used in Qwen3.5. Each GDN head maintains a state matrix. In Agrawal’s setup, the gate is set to 1 so stored values do not fade, the write strength is set to 1 so a write replaces the selected value, and one-hot keys address individual rows. He says this lets the state function as exact, addressable RAM for the CPU’s registers, program counter and memory.
During execution, the model generates tokens that encode memory addresses, values and instruction steps. Those tokens form the CPU’s execution trace as the model runs. Agrawal says the system can perform arithmetic and run C and MicroPython code without an external runtime or tool call, though he describes execution as relatively slow. A small driver called RvChat loads firmware into the GDN state and keeps trace tokens out of the model’s ordinary layers. The report says the model can use a familiar tool-call format to communicate with this internal processor; that format does not mean an external tool is being invoked.
A Processor Runs in Model State
Qwenputer is significant as a proof-of-concept for computation inside model weights, not as a replacement for a physical processor. Its reported design separates the roles usually combined in a conventional computer: neural-network layers perform control and arithmetic operations, while recurrent state holds data in a fixed-size memory structure. That provides a concrete example of a model being configured to execute a defined instruction set rather than simply generating an answer that resembles a calculation.
The claim of determinism matters because exact arithmetic and repeatable state updates are different from asking a language model to reason through a calculation in text. If independently reproduced, the method could help researchers study how recurrent state can support reliable computation, memory and internal monitoring. For now, the report does not establish that this approach is practical for general-purpose computing: the author notes the processor is slow and does not describe it as capable of running a full desktop operating system.
The work also speaks to model oversight. Agrawal points to follow-up experiments involving hidden reasoning in recurrent state and in-model monitoring. Those are related research directions, not results established by the CPU demonstration itself. The reported system shows that the state can be used as computer memory; it does not by itself prove claims about safety, monitoring effectiveness or how a deployed model might behave.
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How Gated DeltaNet Holds Data
Qwen3.5 uses a hybrid architecture in which, according to Agrawal, three of every four attention layers use Gated DeltaNet. In the standard arrangement, a GDN head updates a state matrix as tokens are processed, with its gate controlling how much previous state is retained. The state has a fixed size rather than growing with every token in the way an attention key-value cache does.
The underlying idea of using delta-rule linear attention as associative memory predates Qwenputer. Agrawal cites a 2021 paper by Imanol Schlag, Kazuki Irie and Jürgen Schmidhuber on linear transformers as “fast weight programmers.” He presents the distinctive step in this project as making memory exact and addressable within a production model, then compiling a complete CPU to operate on it. The report says the computer’s weights are set by a compiler, without training the model to create the processor.
Agrawal says Qwenputer’s model files are available through Hugging Face and ModelScope, with code on GitHub. The supplied report does not include independent testing documentation or a publication date, so the performance and compatibility details should be read as the developer’s account.
““The RNN inside Qwen3.5 can be exact RAM.””
— Divyansh Agrawal, Qwenputer’s creator
Independent Tests Still Needed
The reported test results come from Agrawal’s account. He says Qwenputer passes the official RISC-V tests, matches QEMU on programs and completed an 18-million-instruction free-running run without error, but the supplied material does not provide an independent replication, test logs or a full performance evaluation. It is therefore not clear how broadly those results have been checked.
The report also gives no detailed benchmarks for execution speed, memory capacity, energy use or scaling to larger programs. Agrawal says C and MicroPython can run “quite well” but also characterizes the system as slow. The material does not specify which programs were tested, how long they took, or what practical workloads the model can support. The described CPU is not presented as a Linux-class system.
Qwenputer’s ability to use an internal processor without an external tool call is part of the creator’s design description. The report does not establish how the approach behaves across different prompts, model settings or deployment environments, nor does it validate broader claims raised in related work about hidden reasoning or monitoring.
Reproduction and Performance Results
Agrawal points readers to the model files and code as a route to examining or reproducing the experiment. The next useful evidence would include independent runs of the RISC-V test suite, published execution traces, and benchmarks that specify program size, runtime and error rates. Such results could clarify how reliably the processor operates beyond the creator’s reported tests.
Further details on memory limits and performance would show whether the design is mainly a demonstration of in-model computation or can handle longer, more demanding workloads. The supplied report does not announce a release schedule for later versions or an independent evaluation, so those developments remain open.
Key Questions
What is Qwenputer?
Qwenputer is an experimental Qwen3.5 4B model with additional weights that Agrawal says implement a RISC-V CPU inside the model’s forward passes.
Does it call an external CPU or tool?
According to Agrawal, no external processor runtime or tool call executes the program. The model generates instruction-trace tokens, and its added computer layers perform the operations internally.
How does the model provide memory?
The design configures Gated DeltaNet state to hold values without fading and uses one-hot keys to write to or read particular rows, treating that state as addressable RAM.
Has the CPU been independently verified?
The report says it passes official RISC-V tests and completed an 18-million-instruction run without error. The supplied material does not include independent verification, so those remain claims reported by the creator.
Can Qwenputer run ordinary computer programs?
Agrawal says it can run C and MicroPython, but describes it as slow and says it is not a Linux-class system. The report does not provide detailed benchmarks or a list of tested programs.
Source: divagr.com
